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1 file number 2485.7 hsp45116 numerically controlled oscillator/modulator the intersil hsp45116 combines a high performance quadrature numerically controlled oscillator (nco) and a high speed 16-bit complex multiplier/accumulator (cmac) on a single ic. this combination of functions allows a complex vector to be multiplied by the internally generated (cos, sin) vector for quadrature modulation and demodulation. as shown in the block diagram, the hsp45116 is divided into three main sections. the phase/frequency control section (pfcs) and the sine/cosine section together form a complex nco. the cmac multiplies the output of the sine/ cosine section with an external complex vector. the inputs to the phase/frequency control section consist of a microprocessor interface and individual control lines. the phase resolution of the pfcs is 32 bits, which results in frequency resolution better than 0.008hz at 33mhz. the output of the pfcs is the argument of the sine and cosine. the spurious free dynamic range of the complex sinusoid is greater than 90dbc. the output vector from the sine/cosine section is one of the inputs to the complex multiplier/accumulator. the cmac multiplies this (cos, sin) vector by an external complex vector and can accumulate the result. the resulting complex vectors are available through two 20-bit output ports which maintain the 90db spectral purity. this result can be accumulated internally to implement an accumulate and dump filter. a quadrature down converter can be implemented by loading a center frequency into the phase/frequency control section. the signal to be down converted is the vector input of the cmac, which multiplies the data by the rotating vector from the sine/cosine section. the resulting complex output is the down converted signal. features ? nco and cmac on one chip ? 15mhz, 25.6mhz, 33mhz versions ? 32-bit frequency control ? 16-bit phase modulation ? 16-bit cmac ? 0.008hz tuning resolution at 33mhz ? spurious frequency components < -90dbc ? fully static cmos applications ? frequency synthesis ? modulation - am, fm, psk, fsk, qam ? demodulation, pll ? phase shifter ? polar to cartesian conversions block diagram ordering information part number temp. range ( o c) package pkg. no. hsp45116vc-15 0 to 70 160 ld mqfp q160.28x28 hsp45116vc-25 0 to 70 160 ld mqfp q160.28x28 hsp45116gc-15 0 to 70 145 ld cpga g145.a hsp45116gc-25 0 to 70 145 ld cpga g145.a HSP45116GC-33 0 to 70 145 ld cpga g145.a hsp45116gi-15 -40 to 85 145 ld cpga g145.a hsp45116gi-25 -40 to 85 145 ld cpga g145.a hsp45116gi-33 -40 to 85 145 ld cpga g145.a hsp45116gm-15/883 -55 to 125 145 ld cpga g145.a hsp45116gm-25/883 -55 to 125 145 ld cpga g145.a hsp45116avc-52 0 to 70 160 ld mqfp q160.28x28 ? this part has its own data sheet under hsp45116a, answerfax document no. 4156. phase/ frequency control section sine/ cosine section cmac sine/ cosine argument sin cos vector input vector output ri ri microprocessor interface individual control signals data sheet may 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
2 pinouts 145 pin pga top view a b c d e f g h j k l m n p q a b c d e f g h j k l m n p q 123456789101112131415 123456789101112131415 gnd v cc v cc v cc gnd gnd gnd gnd v cc v cc gnd v cc gnd imin imin imin imin imin imin imin imin index rin rin rin rin rin rin rin rin rin rin acc clk ad 1 c 15 c 10 mod 0 enof reg ad 0 c 14 c 13 c 8 c 2 0 314 65 98 71112 23612 5 7 10 13 p a co ro 1 ro 5 ro 8 ro 9 ro 14 io 0 io 3 ro 18 io 2 io 10 io 1 io 4 ro 19 ro 17 ro 16 ro 15 ro 13 ro 11 ro 12 ro 10 ro 7 ro 4 ro 6 ro 2 det 1 ro 3 oerext oei ro 0 oeiext det 0 1 c 3 c 1 oer c 5 c 4 c 0 tico p a ci binfmt peak enph reg mod 1 lo ad clr ofr eni encf reg entireg wr cs modpi / 2pi c 6 c 7 c 11 c 12 sh 1 r by ti ld rin 0 rin 2 sh 0 pmsel enpha c c 9 imin 17 imin 18 io 17 io 13 io 9 io 6 io 5 io 7 io 8 io 11 io 14 io 16 io 19 imin 14 io 18 io 15 io 12 v cc gnd v cc imin 16 imin 4 imin 8 imin 9 imin 11 imin 15 imin 1 rin 18 rin 15 rin 17 rin 13 imin 0 rin 10 rin 14 rin 16 out- mux out- mux hsp45116
3 145 pin pga bottom view pinouts (continued) a b c d e f g h j k l m n p q a b c d e f g h j k l m n p q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gnd v cc v cc v cc gnd gnd gnd gnd v cc v cc gnd v cc gnd imin imin imin imin imin imin imin imin index rin rin rin rin rin rin rin rin rin rin acc clk ad 1 c 15 c 10 mod 0 enof reg ad 0 c 14 c 13 c 8 c 2 0 3 1 4 6 5 9 8 7 11 12 2 3 6 12 5 7 10 13 p a co ro 1 ro 5 ro 8 ro 9 ro 14 io 0 io 3 ro 18 io 2 io 10 io 1 io 4 ro 19 ro 17 ro 16 ro 15 ro 13 ro 11 ro 12 ro 10 ro 7 ro 4 ro 6 ro 2 det 1 ro 3 oerext oei ro 0 oeiext det 0 1 c 3 c 1 oer c 5 c 4 c 0 tico p a ci binfmt peak enph reg mod 1 lo ad clr ofr eni encf reg entireg wr cs modpi / 2pi c 6 c 7 c 11 c 12 sh 1 r by ti ld rin 0 rin 2 sh 0 pmsel enpha c c 9 imin 17 imin 18 io 17 io 13 io 9 io 6 io 5 io 7 io 8 io 11 io 14 io 16 io 19 imin 14 io 18 io 15 io 12 v cc gnd v cc imin 16 imin 4 imin 8 imin 9 imin 11 imin 15 imin 1 rin 18 rin 15 rin 17 rin 13 imin 0 rin 10 rin 14 rin 16 out- mux out- mux hsp45116
4 160lead mqfp top view pinouts (continued) 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 119 120 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 126 127 128 129 130 131 121 122 123 124 125 137 138 139 140 132 133 134 135 136 146 147 148 149 150 151 141 142 143 144 145 157 158 159 160 152 153 154 155 156 ro9 v cc ro8 ro7 ro6 ro5 gnd ro10 ro18 ro17 ro16 ro15 v cc ro13 ro12 ro11 gnd ro14 gnd io6 io5 io4 io3 io2 io1 v cc io0 ro19 gnd gnd ro2 ro1 ro0 det1 det0 gnd v cc ro4 ro3 nc clr ofr encfreg enpha c entireg eni modpi/2pi cs gnd clk v cc ad1 ad0 wr c15 c14 c13 c12 c11 c10 c9 c8 gnd c7 c6 c5 c4 c3 c2 c1 c0 nc outmux1 outmux0 gnd oer v cc oerext oeiext oei p a co mod1 v cc tico gnd rbytild mod0 p a ci lo ad pmsel nc peak rin0 v cc sh1 sh0 acc enphreg enofreg binfmt rin6 rin7 rin8 rin9 rin11 rin5 rin4 rin3 rin2 gnd rin12 rin17 rin18 imin0 rin16 rin15 rin14 gnd rin13 rin10 io7 io8 io9 v cc gnd io10 io11 io12 io13 io14 gnd v cc io15 io16 io17 io18 io19 imin18 imin17 imin16 imin15 imin14 gnd imin13 v cc imin12 imin11 imin10 imin9 nc imin8 imin7 imin6 imin5 imin4 imin3 imin2 gnd imin1 v cc rin1 42 hsp45116
5 pin description name number type description v cc a1, a9, a15, g1, j15, q1, q7, q15 - +5v power supply input. gnd a8, a14, b1, h1, h15, p15, q2, q8 - power supply ground input. c0-15 n8-11, p8-13, q9-14 i control input bus for loading phase and frequency data into the pfcs. c15 is the msb. ad0-1 n7, p7 i address pins for selecting destination of c0-15 data. cs p6 i chip select (active low). wr q6 i write enable. data is clocked into the register selected by ad0-1 on the rising edge of wr when the cs line is low. clk q5 i clock. all registers, except the control registers clocked with wr, are clocked (when enabled) by the rising edge of clk. enphreg m1 i phase register enable (active low). registered on chip by clk. when active, after being clocked onto chip, enphreg enables the clocking of data into the phase register. enofreg n1 i frequency offset register enable (active low). registered on chip by clk. when active, after being clocked onto chip, enofreg enables clocking of data into the frequency offset register. encfreg n5 i center frequency register enable (active low). registered on chip by clk. when active, after being clocked onto chip, encfreg enables clocking of data into the center frequency register. enpha c q3 i phase accumulator register enable (active low). registered on chip by clk. when active, after being clocked onto chip, enpha c enables clocking of the phase accumulator register. entireg p5 i time interval control register enable (active low). registered on chip by clk. when active, after being clocked onto chip, entireg enables clocking of data into the time accumulator register. eni q4 i real and imaginary data input register (rir, iir) enable (active low). registered on chip by clk. when active, after being clocked onto chip, eni enables clocking of data into the real and imaginary input data register. modpi/ 2pi n6 i modulo p /2 p select. when low, the sine and cosine roms are addressed modulo 2 p (360 degrees). when high, the most signi?cant address bit is held low so that the roms are addressed modulo p (180 degrees). this input is registered on chip by clock. clr ofr p4 i frequency offset register output zero (active low). registered on chip by clk. when active, after being clocked onto chip, clr ofr zeros the data path from the frequency offset register to the frequency adder. new data can still be clocked into the frequency offset register; clr ofr does not affect the contents of the register. lo ad n4 i phase accumulator load control (active low). registered on chip by clk. zeroes feedback path in the phase accumulator without clearing the phase accumulator register. mod0-1 m3, n3 i external modulation control bits. when selected with the pmsel line, these bits add a 0, 90, 180, or 270 degree offset to the current phase in the phase accumulator. the lower 14 bits of the phase control path are set to zero. these bits are loaded into the phase register when enphreg is low. pmsel p3 i phase modulation select line. this line determines the source of the data clocked into the phase register. when high, the phase control register is selected. when low, the external modulation pins (mod0-1) are selected for the most significant two bits and the least significant two bits and the least significant 14 bits are set to zero. this control is registered by clk. rbytild l3 i rom bypass, timer load. active low, registered by clk. this input bypasses the sine/ cosine rom so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go directly to the cmacs sine and cosine inputs, respectively. it also enables loading of the timer accumulator register by zeroing the feedback in the accumulator. p a ci p2 i phase accumulator carry input (active low). a low on this pin causes the phase accumulator to increment by one, in addition to the values in the phase accumulator register and frequency adder. hsp45116
6 p a co l13 o phase accumulator carry output. active low and registered by clk. a low on this output indicates that the phase accumulator has over?owed, i.e., the end of one sine/cosine cycle has been reached. tico p1 o time interval accumulator carry output. active low, registered by clk. this output goes low when a carry is generated by the time interval accumulator. this function is provided to time out control events such as synchronizing register clocking to data timing. rin0-18 c1, c2, d1, d2, e1- 3, f1-3, g2, g3, h2, h3, j1-3, k1, k2 i real input data bus. this is the external real component into the complex multiplier. the bus is clocked into the real input data register by clk when eni is asserted; twos complement. imin0-18 a2-7, b2-7, c3-8, d3 i imaginary input data bus. this is the external imaginary component into the complex multiplier. the bus is clocked into the real input data register by clk when eni is asserted; twos complement. sh0-1 k3, l1 i shift control inputs. these lines control the input shifters of the rin and iin inputs of the complex multiplier. the shift controls are common to the shifters on both of the busses. acc l2 i accumulate/dump control. this input controls the complex accumulators and their holding registers. when high, the accumulators accumulate and the holding registers are disabled. when low, the feedback in the accumulators is zeroed to cause the accumulators to load. the holding registers are enabled to clock in the results of the accumulation. this input is registered by clk. binfmt n2 i this input is used to convert the twos complement output to offset binary (unsigned) for applications using d/a converters. when low, bits ro19 and io19 are inverted from the internal twos complement representation. this input is registered by clk. peak m2 i this input enables the peak detect feature of the block ?oating point detector. when high, the maximum bit growth in the output holding registers is encoded and output on the det0-1 pins. when the peak input is asserted, the block ?oating point detector output will track the maximum growth in the holding registers, including the data in the holding registers at the time that peak is activated. outmux0-1 n12, n13 i these inputs select the data to be output on ro0-19 and io0-19. ro0-19 c15, d14, d15, e14, e15, f13-15, g13-15, h13, h14, j13, j14, k13-15, l15, m15 o real output data bus. these three-state outputs are controlled by oer and oerext. outmux0-1 select the data output on the bus. io0-19 a10-13, b8-15, c9- 14, d13, e13 o imaginary output data bus. these three-state outputs are controlled by oei and oeiext. outmux0-1 select the data output on the bus. det0-1 n15, l14 o these output pins indicate the number of bits of growth in the accumulators. while peak is low, these pins indicate the peak growth. the detector examines bits 15-18, real and imaginary accumulator holding registers and bits 30-33 of the real and imaginary cmac holding registers. the bits indicate the largest growth of the four registers. oer p14 i three-state control for bits ro0-15. outputs are enabled when the line is low. oerext m13 i three-state control for bits ro16-19. outputs are enabled when the line is low. oei m14 i three-state control for bits io0-15. outputs are enabled when the line is low. oeiext n14 i three-state control for bits io16-19. outputs are enabled when the line is low. pin description (continued) name number type description hsp45116
7 functional block diagram cos sin 16 r.rbytild r.pmsel r.enphreg r e g > clk 16 p a ci 32 phase input register ms input register 16 14 phen 0 16 r.enphreg ls input register lsen offset register center frequency register r.pmsel frequency adder a d d e r 2 16 phase register 16 16 32 32 32 32 r.clr ofr 32 32 32 msen clk 32 r.encf reg r.lo ad r.enofreg 0 0 mod(1:0) encode c(15:0) phase accumulator adder 0 phase adder sin/cos argument a d d e r 32 16 msbs 16 16 lsbs p a co r.modpi/2pi msb 15 r.enpha c a d d e r 32 phase accumulator register phase accumulator decoder r.encfreg r.enofreg r.clr ofr r.lo ad r.enpha c r.modpi/2pi pmsel encfreg clr ofr lo ad enphreg enpha c modpi/2pi enofreg clk time increment 32 0 r.entireg 32 32 32 carry out time accumulator register r.rbytild tico adder 32 ad(1:0) cs wr entireg rbytild r.entireg acc r.eni eni r.binfmt binfmt r.sh(1:0) sh(1:0) peak r.peak sine/cosine generator 20 32 32 16 16 16 time accumulator outmux(1:0) oerext oer oeiext oei tico p a co rin(18:0) imin(18:0) clk phase r.acc r.eni r.binfmt r.sh(1:0) r.peak r.acc frequency r e g > r e g > r e g > r e g > r e g > clk r e g > clk r e g > clk r e g > clk clk r e g > r e g > clk clk r e g > r e g > clk r e g > clk p a ci r e g > 0 1 mux 1 0 mux 0 1 mux 0 1 mux 1 0 mux rin(18:0) imin(18:0) hsp45116
8 functional block diagram (continued) 3 adder r1.acc 0 0 16 16 shifter shifter r.sh(1:0) r.eni 19 19 sin 16 cos 16 complex multiplier 33 33 adder adder 0 adder complex accumulator cmac accumulator r.peak 0 growth detect det(1:0) 16 3 fmt 16 4 outmux(1:0) ro(19-16) ro(15:0) r.binfmt oerext oer 16 fmt 16 4 outmux(1:0) io(19-16) io(15:0) r.binfmt oeiext oei 35 35 20 20 r1.acc r2.acc round 0 round rin0-18 imin0-18 r.rbytild r.eni r.sh(1:0) sin cos r.acc r.peak r.sh(1:0) r.eni outmux(1:0) see table 4 clk r e g > clk r e g > reg > clk reg > clk reg > clk reg > clk r e g > clk r e g > clk reg > clk reg > clk reg > clk clk reg < reg > clk clk reg < reg > clk reg > clk reg < clk reg > clk reg < clk 0 1 mux 1 0 mux mux 0 1 mux 0 1 mux mux outmux(1:0) see table 4 1 0 mux clk reg < clk reg < 1 0 mux phase rin(18:0) imin(18:0) hsp45116
9 functional description the numerically controlled oscillator/modulator (ncom) produces a digital complex sinusoid waveform whose amplitude, phase and frequency are controlled by a set of input command words. when used as a numerically controlled oscillator (nco), it generates 16-bit sine and cosine vectors at a maximum sample rate of 33mhz. the ncom can be preprogrammed to produce a constant (cw) sine and cosine output for direct digital synthesis (dds) applications. alternatively, the phase and frequency inputs can be updated in real time to produce a fm, psk, fsk, or msk modulated waveform. the complex multiplier/ accumulator (cmac) can be used to multiply this waveform by an input signal for am and qam signals. by stepping the phase input, the output of the rom becomes an fft twiddle factor; when data is input to the vector inputs (see block diagram), the ncom calculates an fft butter?y. as shown in the block diagram, the ncom consists of three parts: phase and frequency control section (pfcs), sine/cosine generator, and cmac. the pfcs stores the phase and frequency inputs and uses them to calculate the phase angle of a rotating complex vector. the sine/cosine generator performs a lookup on this phase and outputs the appropriate values for the sine and cosine. the sine and cosine form one set of inputs to the cmac, which multiplies them by the input vector to form the modulated output. phase and frequency control section the phase and frequency of the internally generated sine and cosine are controlled by the pfcs (block diagram). the pfcs generates a 32-bit word that represents the current phase of the sine and cosine waves being generated; the sine/ cosine argument. stepping this phase angle from 0 through full scale (2 32 - 1) corresponds to the phase angle of a sinusoid starting at 0 o and advancing around the unit circle counterclockwise. the pfcs automatically increments the phase by a preprogrammed amount on every rising edge of the external clock. the value of the phase step (which is the sum of the center and offset frequency registers) is: the pfcs is divided into two sections: the phase accumulator uses the data on c0-15 to compute the phase angle that is the input to the sine/cosine section (sine/cosine argument); the time accumulator supplies a pulse to mark the passage of a preprogrammed period of time. the phase accumulator and time accumulator work on the same principle: a 32-bit word is added to the contents of a 32-bit accumulator register every clock cycle; when the sum causes the adder to over?ow, the accumulation continues with the 32 bits of the adder going into the accumulator register. the over?ow bit is used as an output to indicate the timing of the accumulation over?ows. in the time accumulator, the over?ow bit generates tico, the time accumulator carry out (which is the only output of the time accumulator). in the phase accumulator, the over?ow is inverted to generate the phase accumulator carry out, p a co. the output of the phase accumulator goes to the phase adder, which adds an offset to the top 16 bits of the phase. this 32-bit number forms the argument of the sine and cosine, which is passed to the sine/cosine generator. both accumulators are loaded 16 bits at a time over the c0-15 bus. data on c0-15 is loaded into one of the three input registers when cs and wr are low. the data in the most signi?cant input register and least signi?cant input register forms a 32-bit word that is the input to the center frequency register, offset frequency register and time accumulator. these registers are loaded by enabling the proper register enable signal; for example, to load the center frequency register, the data is loaded into the ls and ms input registers, and encfreg is set to zero; the next rising edge of clk will pass the registered version of encfreg, r.encfreg, to the clock enable of the center frequency register; this register then gets loaded on the following rising edge of clk. the contents of the input registers will be continuously loaded into the center frequency register as long as r.encfreg is low. the phase register is loaded in a similar manner. assuming pmsel is high, the contents of the phase input register is loaded into the phase register on every rising clock edge that r.enphreg is low. if pmsel is low, mod0-1 supply the two most signi?cant bits into the phase register (mod1 is the msb) and the least signi?cant 14 bits are loaded with 0. mod0-1 are used to generate a quad phase shift keying (qpsk) signal (table 2). the phase accumulator consists of registers and adders that compute the value of the current phase at every clock. it has three inputs: center frequency, which corresponds to the carrier frequency of a signal; offset frequency, which is the deviation from the center frequency; and phase, which is a 16-bit number that is added to the current phase for psk phase step = signal frequency clock frequency ---------------------------------------------- 2 32 table 1. ad0-1 decoding ad1 ad0 cs wr function 000 - load least significant bits of frequency input. 010 - load most significant bits of frequency input. 100 - load phase register. 1 1 x x reserved. x x 1 x no operation. hsp45116
10 modulation schemes. these three values are used by the phase accumulator and phase adder to form the phase of the internally generated sine and cosine. the sum of the values in center and offset frequency registers corresponds to the desired phase increment (modulo 2 32 ) from one clock to the next. for example, loading both registers with zero will cause the phase accumulator to add zero to its current output; the output of the pfcs will remain at its current value; i.e., the output of the ncom will be a dc signal. if a hexadecimal 00000001 is loaded into the center frequency control register, the output of the pfcs will increment by one after every clock. this will step through every location in the sine/cosine generator, so that the output will be the lowest frequency above dc that can be generated by the ncom, i.e., the clock frequency divided by 2 32 . if the input to the center frequency control register is hex 80000000, the pfcs will step through the generator with half of the maximum step size, so that frequency of the output waveform will be half of the sample rate. the operation of the offset frequency control register is identical to that of the center frequency control register; having two separate registers allows the user to generate an fm signal by loading the carrier frequency in the center frequency control register and updating the offset frequency control register with the value of the frequency offset - the difference between the carrier frequency and the frequency of the output signal. a logic low on clr ofr disables the output of the offset frequency register without clearing the contents of the register. initializing the phase accumulator register is done by putting a low on the lo ad line. this zeroes the feedback path to the accumulator, so that the register is loaded with the current value of the phase increment summer on the next clock. the ?nal phase value going to the generator can be adjusted using modpi/ 2pi to force the range of the phase to be 0 o to 180 o (modulo p )or0 o to 360 o (modulo 2 p ). modulo 2 p is the mode used for modulation, demodulation, direct digital synthesis, etc. modulo p is used to calculate ffts. this is explained in greater detail in the applications section. the phase register adds an offset to the output of the phase accumulator. since the phase register is only 16 bits, it is added to the top 16 bits of the phase accumulator. the time accumulator consists of a register which is incremented on every clock. the amount by which it increments is loaded into the input registers and is latched into the time accumulator register on rising edges of clk while entireg is low. the output of the time accumulator is the accumulator carry out, tico. tico can be used as a timer to enable the periodic sampling of the output of the ncom. the number programmed into this register equals 2 32 x clk period/desired time interval. tico is disabled and its phase is initialized by zeroing the feedback path of the accumulator with rbytild. sine/cosine section the sine/cosine section (figure 1) converts the output of the pfcs into the appropriate values for the sine and cosine. it takes the most signi?cant 20 bits of the pfcs output and passes them through a look up table to form the 16-bit sine and cosine inputs to the cmac. the 20-bit word maps into 2 p radians so that the angular resolution is 2 p /2 20 . an address of zero corresponds to 0 radians and an address of hex fffff corresponds to 2 p -(2 p /2 20 ) radians. the outputs of the generator section are 2s complement sine and cosine values. the sine and cosine outputs range from hexadecimal 8001, which represents negative full scale, to 7fff, which represents positive full scale. note that the normal range for twos complement numbers is 8000 to 7fff; the output range of the sin/cos generator is scaled by one so that it is symmetric about 0. the sine and cosine values are computed to reduce the amount of rom needed. the magnitude of the error in the computed value of the complex vector is less than -90.2db. the error in the sine or cosine alone is approximately 2db better. if rbytild is low, the output of the pfcs goes directly to the inputs of the cmac. if the real and imaginary inputs of the cmac are programmed to hex 7fff and 0 respectively, then the output of the pfcs will appear on output bits 0 through 15 of the ncom with the output multiplexers set to bring out the most signi?cant bits of the cmac output (outmux = 00). the most signi?cant 16 bits out of the pfcs appears on iout0-15 and the least signi?cant bits come out on rout0-15. table 2. mod0-1 decode mod1 mod0 phase shift (degrees) 00 0 01 90 1 0 270 1 1 180 clk sine/cosine generator 20 sin/cos argument 32 32 reg clk r.rbytild mux cos 16 sin 16 16 16 16 16 figure 1. sine/cosine section hsp45116
11 complex multiplier/accumulator the cmac (figure 2) performs two types of functions: complex multiplication/accumulation for modulation and demodulation of digital signals, and the operations necessary to implement an fft butter?y. modulation and demodulation are implemented using the complex multiplier and its associated accumulator; the rest of the circuitry in this section, i.e., the complex accumulator, input shifters and growth detect logic are used along with the complex multiplier/accumulator for ffts. the complex multiplier performs the complex vector multiplication on the output of the sine/cosine section and the vector represented by the real and imaginary inputs rin and iin. the two vectors are combined in the following manner: rout = cos x rin - sin x iin iout = cos x iin + sin x rin rin and iin are latched into the input registers and passed through the shift stages. clocking of the input registers is enabled with a low on eni. the amount of shift on the latched data is programmed with sh0-1 (table 3). the output of the shifters is sent to the cmac and the auxiliary accumulators. the 33-bit real and imaginary outputs of the complex multiplier are latched in the multiplier registers and then go through the accumulator section of the cmac. if the acc line is high, the feedback to the accumulators is enabled; a low on acc zeroes the feedback path, so that the next set of real and imaginary data out of the complex multiplier is stored in the cmac output registers. the data in the cmac output registers goes to the multiplexer, the output of which is determined by the outmux0-1 lines (table 4). binfmt controls whether the output of the multiplexer is presented in twos complement or unsigned format; binfmt = 0 inverts rout19 and iout19 for unsigned output, while binfmt = 1 selects twos complement. the complex accumulator duplicates the accumulator in the cmac. the input comes from the data shifters, and its 20-bit complex output goes to the multiplexer. acc controls whether the accumulator is enabled or not. outmux0-1 determines whether the accumulator output appears on rout and iout. table 3. input shift selection sh1 sh0 selected bits 0 0 rin0-15, imin0-15 0 1 rin1-16, imin1-16 1 0 rin2-17, imin2-17 1 1 rin3-18, imin3-18 table 4. output multiplexer selection out mux 1 out mux 0 ro16-19 ro0-15 io16-19 io0-15 0 0 real cmac 31-34 real cmac 15-30 imag cmac 31-34 imag cmac 15-30 0 1 real cmac 31-34 0, real cmac 0-14 imag cmac 31-34 0, imag cmac 0-14 1 0 real acc 16-19 real acc 0-15 imag acc 16-19 imag acc 0-15 1 1 reserved reserved reserved reserved hsp45116
12 mux mux adder reg r1.acc 00 reg reg reg 16 16 reg reg shifter shifter rin0-18 imin0-18 r.sh0-1 r.eni 19 19 reg sin 16 reg cos 16 complex multiplier 33 33 reg reg adder adder r2.acc mux reg 0 mux reg adder reg reg complex accumulator cmac accumulator mux r.peak 0 growth detect reg det0-1 16 3 fmt mux 16 4 outmux0-1 ro16-19 ro0-15 r.binfmt oerext oer 16 3 fmt mux 16 4 outmux0-1 io16-19 io0-15 r.binfmt oeiext oei 35 35 20 20 reg reg reg r1.acc acc r.eni eni r1.acc r2.acc reg reg reg r.binfmt binfmt r.sh0-1 sh0-1 peak r.peak reg 0 figure 2. complex multiplier/accumulator; all registers clocked by clk hsp45116
13 the growth detect circuitry outputs a two bit value that signi?es the amount of growth on the data in the cmac and complex accumulator. its output, det0-1, is encoded as shown in table 5. if peak is low, the highest value of det0-1 is latched in the growth detect output register. the relative weighting of the bits at the inputs and outputs of the cmac is shown in figure 3. note that the binary point of the sine, cosine, rin and iin is to the right of the most signi?cant bit, while the binary point of ro and io is to the right of the ?fth most signi?cant bit. these cmac external input and output busses are aligned with each other to facilitate cascading ncoms for fft applications. figure 3. bit weighting table 5. growth encoding det 1 det 0 number of bits of growth above 2 o 00 0 01 1 10 2 11 3 sin/cos input 1514131211109876543210 -2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 - radix point complex multiplier/accumulator input (rin, iin) sh = 00 1514131211109876543210 -2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 - radix point complex multiplier/accumulator output (ro, io) outmux = 00 191817161514131211109876543210 -2 4 2 3 2 2 2 1 -2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 - radix point complex multiplier/accumulator output (ro, io) outmux = 01 191817161514131211109876543210 -2 4 2 3 2 2 2 1 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 2 -25 2 -26 2 -27 2 -28 2 -29 2 -30 0 complex accumulator output (ro, io) outmux = 10 191817161514131211109876543210 -2 4 2 3 2 2 2 1 -2 0 . 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 - radix point hsp45116
14 applications the ncom can be used for amplitude, phase and frequency modulation, as well as in variations and combinations of these techniques, such as qam. it is most effective in applications requiring multiplication of a rotating complex sinusoid by an external vector. these include am and qam modulators and digital receivers. the ncom implements am and qam modulation on a single chip, and is a element in demodulation, where it performs complex down conversion. it can be combined with the intersil hsp43220 decimating digital filter to form the front end of a digital receiver. modulation/demodulation figure 4 shows a block diagram of an am modulator. in this example, the phase increment for the carrier frequency is loaded into the center frequency register, and the modulating input is clocked into the real input of the cmac, with the imaginary input set to 0. the modulated output is obtained at the real output of the cmac. with a sixteen bit, twos complement signal input, the output will be a 16-bit real number, on rout0-15 (with outmux = 00). by replacing the real input with a complex vector, a similar setup can generate qam signals (figure 5). in this case, the carrier frequency is loaded into the center frequency register as before, but the modulating vector now carries both amplitude and phase information. since the input vector and the internally generated sine and cosine waves are both 16 bits, the number of states is only limited by the characteristics of the transmission medium and by the analog electronics in the transmitter and receiver. the phase and amplitude resolution for the sine/cosine section (16-bit output), delivers a spectral purity of greater than 90dbc. this means that the unwanted spectral components due to phase uncertainty (phase noise) will be greater than 90db below the desired output (dbc, decibels below the carrier). with a 32-bit phase accumulator in the phase/frequency control section, the frequency tuning resolution equals the clock frequency divided by 2 32 . for example, a 25mhz clock gives a tuning resolution of 0.006hz. the ncom also works with the hsp43220 decimating digital filter to implement down conversion and low pass ?ltering in a digital receiver (figure 6). the ncom performs complex down conversion on the wideband input signal by multiplying the input vector and the internally generated complex sinusoid. the resulting signal has components at twice the center frequency and at dc. two hsp43220s, one each on the real and imaginary outputs of the hsp45116, perform low pass ?ltering and decimation on the down converted data, resulting in a complex baseband signal. figure 4. amplitude modulation clk ncom modulated output pfcs 32 center frequency sin 16 sine/cosine generator cmac rin signal input 16 ro 16 d/a xmtr lo figure 5. quadrature amplitude modulation (qam) clk ncom pfcs 32 center frequency sine/cosine generator cmac ro 16 d/a rin 16 imin 16 xmtr lo 16 16 figure 6. channelized receiver chip set hsp43220 ddf hsp45116 ncom cos (wt) sin (wt) sampled input data 0 10mhz ddf output ncom output input 0 20mhz 0 hsp45116
15 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied . . . . .gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range. . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v operating temperature range . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) mqfp package . . . . . . . . . . . . . . . . . . 22.0 n/a pga package. . . . . . . . . . . . . . . . . . . . 23.1 3 maximum junction temperature mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c pga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (mqfp - lead tips only) die characteristics component count . . . . . . . . . . . . . . . . . . . . . . . 103,000 transistors caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v high level clock input v ihc v cc = 5.25v 3.0 - v low level clock input v ilc v cc = 4.75v - 0.8 v output high voltage v oh i oh = -400ma, v cc = 4.75v 2.6 - v output low voltage v ol i ol = 2.0ma, v cc = 4.75v - 0.4 v input leakage current i i v in = v cc or gnd, v cc = 5.25v -10 10 m a i/o leakage current i o v out = v cc or gnd, v cc = 5.25v -10 10 m a standby power supply current i ccsb v in = v cc or gnd v cc = 5.25v, note 4 - 500 m a operating power supply current i ccop f = 15mhz, v in = v cc or gnd, v cc = 5.25v, notes 2 and 4 - 182 ma capacitance t a = 25 o c, note 3 parameter symbol test conditions min max units input capacitance c in freq = 1mhz, v cc = open, all measurements are referenced to device ground -15pf output capacitance c o -15pf notes: 2. power supply current is proportional to operating frequency. typical rating for i ccop is 10ma/mhz. 3. not tested, but characterized at initial design and at major process/design changes. 4. output load per test load circuit with switch open and c l = 40pf. hsp45116
16 ac electrical speci?cations v cc = 5.0v 5%, t a = 0 o c to 70 o c (note 5) parameter symbol notes -15 (15mhz) -25 (25.6mhz) -33 (33mhz) units min max min max min max clk period t cp 66-39-30- ns clk high t ch 26-15-12- ns clk low t cl 26-15-12- ns wr low t wl 26-15-12- ns wr high t wh 26-15-12- ns setup time; ad0-1, cs to wr going high t aws 18-13-13- ns hold time; ad0, ad1, cs from wr going high t awh 0-0-0- ns setup time c0-15 from wr going high t cws 20-15-15- ns hold time c0-15 from wr going high t cwh 0-0-0- ns setup time wr high to clk high t wc 7 20-16-12- ns setup time mod0-1 to clk going high t mcs 20-15-15- ns hold time mod0-1 from clk going high t mch 0-0-0- ns setup time p a ci to clk going high t pcs 25-15-11- ns hold time p a ci from clk going high t pch 0-0-0- ns setup enphreg, encfreg, enofreg, enpha c, entireg, clr ofr, pmsel, lo ad, eni, acc, binfmt, peak, modpi/ 2pi, sh0-1, rbytild from clk going high t ecs 18-12-12- ns hold time enphreg, encfreg, enofreg, en- pha c, entireg, clr ofr, pmsel, lo ad, eni, acc, binfmt, peak, modpi/ 2pi, sh0-1, rbytild from clk going high t ech 0-0-0- ns setup time rin0-18, imin0-18 to clk going high t ds 18-12-12- ns hold time rin0-18, imin0-18 from clk going high t dh 0-0-0- ns clk to output delay ro0-19, io0-19 t do -40-24-19ns clk to output delay det0-1 t deo -40-27-20ns clk to output delay p a co t po -30-20-12ns clk to output delay tico t to -30-20-12ns output enable time oer, oei, oerext, oeiext t oe -25-20-20ns outmux0-1 to output delay t md -40-28-26ns output disable time t od 6 -20-15-15ns output rise, fall time t rf 6 -8-8-6ns notes: 5. ac testing is performed as follows: input levels (clk input) 4.0v and 0v; input levels (all other inputs) 0v and 3.0v; timing reference levels (clk) 2.0v; all others 1.5v. output load per test load circuit with switch closed and c l = 40pf. output transition is measured at v oh 3 1.5v and v ol 1.5v. 6. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. 7. applicable only when outputs are being monitored and encfreg, enphreg, or entireg is active. hsp45116
17 ac test load circuit waveforms figure 7. input and output timing equivalent circuit c l (note) i oh 1.5v i ol dut switch s1 open for i ccsb and i ccop s 1 note: test head capacitance. clk mod0-1 p a ci tico det0-1 p a co rout0-19 iout0-19 control inputs t ch t cp t pcs t mcs t ecs t ds t cl t mch t pch t ech t dh t do t deo t po t to rin0-19 iin0-19 hsp45116
18 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 figure 8. control bus timing figure 9. output enable, disable timing figure 10. multiplexer timing figure 11. output rise and fall times waveforms (continued) t wl t wc t wh t awh t aws t awh t aws t cwh t cws clk cs wr c0-15 ad0-1 high impedance 1.5v t oe 1.7v 1.3v high impedance 1.5v t od ro0-19 io0-19 oer oerext oeiext oei t md outmux0-1 ro0-19 io0-19 2.0v 0.8v t rf t rf hsp45116

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